Verilog HDL: Exploring Different Modelling Styles
When you think of any sequential or combination circuit, what modelling aspects come to mind?
- Truth table
- And logical expression
Similarly, when it’s about Verilog HDL, three modelling aspects come to mind:
- Data flow
These three modelling styles of Verilog HDL are related to the three previously mentioned modelling aspects of the digital circuit. Let’s see how.
Verilog HDL is a language that empowers developers to design a particular module in different coding styles. Based on the requirements of the project, three abstraction levels can be utilized to define the module. However, irrespective of the type of abstraction used internally, the interaction with the external environment remains the same.
Different Types of Modelling in Verilog HDL
Structural Modelling Style
The structural modelling style is the lowest level of abstraction obtained using logic gates. Similar to schematic or circuit diagrams of the digital circuit, Verilog uses primitive gates to compile and synthesize the program.
Of course, this abstraction can’t be understood by humans. Machines, however, have the definite capability of compiling and logically synthesizing the code.
The language supports multiple gates such as and, or, nand, xor, nor, and xnor. You can also use tri-state gates and multiple-output gates such as bufif1, bufif0, notif1, notif0, not, and buf.
Here’s the syntax of these gates:
- and | or | nand | xor | nor | xnor [instance name] (output, input1, ….., inputn);
- not | buf [instance name] (output 1, output2, ….., output n, input);
- bufif1 | bufif0 | notif1 | notif0 [instance name] (output, input, control);
Behavioural Modelling Style
Behavioural modelling is the highest of level abstraction that completely depends on the circuit behaviour or on the truth table.
If you know how your circuit will behave, you can design it. In fact, you can design the module without knowing the components of the hardware.
However, even though it is the closest in terms of natural language understanding of the circuit functionality, this modelling type is hardest to implement and synthesize. Hence, it is utilized for complex circuits such as pure combinational or sequential circuits.
A module developed using behavioural modelling contains initial or always statements, which are executed concurrently (according to the parallelism of the model). The procedural statements in the module are executed sequentially.
At time=0, both the initial and always will execute and then, always statements run for the remaining time. Here’s the syntax:
always [timing control] procedural_statements;
initial [ timing control] procedural_statements;
Data Flow Modelling Style
The data flow is a medium level abstraction, which is achieved by defining the data flow of the module. You can design the module by defining and expressing input signals which are assigned to the output, very much similar to logical expressions.
For most of the modules, data flow modelling is simple to implement and can be easily translated to structure such as in the case of combinational circuits.
The combinational circuits use continuous assignments, where value is defined for a data net.
assign[delay] LHS_net = RHS_expression
All the Verilog HDL modelling styles are utilized for different requirements and purposes. While you can use a data flow model or structural model for combinational circuits, behavioural model is best suited for sequential or combination circuits. Evaluate your requirements first and then select one of the models for maximum output.