Digital System Design using Verilog
Verilog is the most commonly used HDL in design, verification and synthesis of electronic systems
Created by Abhay Chopde
This course provides an overview of the Verilog hardware description language (HDL) and its use in programmable logic design. The emphasis is on the synthesizable constructs of Verilog HDL; however, the trainee will also learn about other simulation constructs which are useful in testing/verifying the design. The course has an extensive laboratory/project work in Verilog simulator.